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	DACS: Transport Control Module
	Transport Control Module The VHDL code for the transport control decode GAL is shown below: ----------------------------------------------------------------------------- -- DACS : Distributed Audio Control System -- -- Copyright (C) 1997 Stephen Scott Richardson ----------------------------------------------------------------------------- -- File: transp.vhd -- Date: 03.13.97 -- Target: Atmel ATF16V8B ----------------------------------------------------------------------------- -- Transport control board pbus address decoding GAL -- -- pbus addx function dir (from uC) -- ================================================== -- 0x17 7 segment 1 ena out -- 0x18 7 segment 2 ena out -- 0x19 7 segment 3 ena out -- 0x20 led enable out -- 0x33 button nena in -- 0x50 encoder nena in ----------------------------------------------------------------------------- ENTITY transp_decode IS PORT ( addx_in : IN bit_vector (6 DOWNTO 0); nlatch_in : IN bit; nread_write_in : IN bit; seg7_1_ena_out : OUT bit; seg7_2_ena_out : OUT bit; seg7_3_ena_out : OUT bit; led_ena_out : OUT bit; btn_nena_out : OUT bit; enc_nena_out : OUT bit; nsense_out : OUT bit ); -- Force package and pinout ATTRIBUTE part_name of transp_decode:entity is "C16V8"; ATTRIBUTE pin_numbers of transp_decode:entity is "nread_write_in:1 nlatch_in:2 addx_in(0):3 addx_in(1):4 addx_in(2):5 addx_in(3):6 addx_in(4):7 addx_in(5):8 addx_in(6):9 nsense_out:12 led_ena_out:13 seg7_3_ena_out:14 enc_nena_out:15 btn_nena_out:16 seg7_2_ena_out:17 seg7_1_ena_out:18"; END transp_decode; ARCHITECTURE behavior OF transp_decode IS BEGIN PROCESS (nlatch_in, addx_in, nread_write_in) BEGIN IF nlatch_in = '0' AND nread_write_in = '1' AND addx_in = "0010111" THEN -- pbus 0x17 nsense_out <= '0'; -- pbus nsense ACTIVE seg7_1_ena_out <= '1'; -- 7seg 1 ena ACTIVE seg7_2_ena_out <= '0'; -- 7seg 2 ena INACTIVE btn_nena_out <= '1'; -- btn nena INACTIVE enc_nena_out <= '1'; -- enc nena INACTIVE seg7_3_ena_out <= '0'; -- 7seg 3 ena INACTIVE led_ena_out <= '0'; -- led ena INACTIVE ELSIF nlatch_in = '0' AND nread_write_in = '1' AND addx_in = "0011000" THEN -- pbus 0x18 nsense_out <= '0'; -- pbus nsense ACTIVE seg7_1_ena_out <= '0'; -- 7seg 1 ena INACTIVE seg7_2_ena_out <= '1'; -- 7seg 2 ena ACTIVE btn_nena_out <= '1'; -- btn nena INACTIVE enc_nena_out <= '1'; -- enc nena INACTIVE seg7_3_ena_out <= '0'; -- 7seg 3 ena INACTIVE led_ena_out <= '0'; -- led ena INACTIVE ELSIF nlatch_in = '0' AND nread_write_in = '0' AND addx_in = "0110011" THEN -- pbus 0x33 (read) nsense_out <= '0'; -- pbus nsense ACTIVE seg7_1_ena_out <= '0'; -- 7seg 1 ena INACTIVE seg7_2_ena_out <= '0'; -- 7seg 2 ena INACTIVE btn_nena_out <= '0'; -- btn nena ACTIVE enc_nena_out <= '1'; -- enc nena INACTIVE seg7_3_ena_out <= '0'; -- 7seg 3 ena INACTIVE led_ena_out <= '0'; -- led ena INACTIVE ELSIF nlatch_in = '0' AND nread_write_in = '0' AND addx_in = "1010000" THEN -- pbus 0x50 (read) nsense_out <= '0'; -- pbus nsense ACTIVE seg7_1_ena_out <= '0'; -- 7seg 1 ena INACTIVE seg7_2_ena_out <= '0'; -- 7seg 2 ena INACTIVE btn_nena_out <= '1'; -- btn nena INACTIVE enc_nena_out <= '0'; -- enc nena ACTIVE seg7_3_ena_out <= '0'; -- 7seg 3 ena INACTIVE led_ena_out <= '0'; -- led ena INACTIVE ELSIF nlatch_in = '0' AND nread_write_in = '1' AND addx_in = "0011001" THEN -- pbus 0x19 nsense_out <= '0'; -- pbus nsense ACTIVE seg7_1_ena_out <= '0'; -- 7seg 1 ena INACTIVE seg7_2_ena_out <= '0'; -- 7seg 2 ena INACTIVE btn_nena_out <= '1'; -- btn nena INACTIVE enc_nena_out <= '1'; -- enc nena INACTIVE seg7_3_ena_out <= '1'; -- 7seg 3 ena ACTIVE led_ena_out <= '0'; -- led ena INACTIVE ELSIF nlatch_in = '0' AND nread_write_in = '1' AND addx_in = "0100000" THEN -- pbus 0x20 nsense_out <= '0'; -- pbus nsense ACTIVE seg7_1_ena_out <= '0'; -- 7seg 1 ena INACTIVE seg7_2_ena_out <= '0'; -- 7seg 2 ena INACTIVE btn_nena_out <= '1'; -- btn nena INACTIVE enc_nena_out <= '1'; -- enc nena INACTIVE seg7_3_ena_out <= '0'; -- 7seg 3 ena INACTIVE led_ena_out <= '1'; -- led ena ACTIVE ELSE -- not active nsense_out <= '1'; -- pbus nsense INACTIVE seg7_1_ena_out <= '0'; -- 7seg 1 ena INACTIVE seg7_2_ena_out <= '0'; -- 7seg 2 ena INACTIVE btn_nena_out <= '1'; -- btn nena INACTIVE enc_nena_out <= '1'; -- enc nena INACTIVE seg7_3_ena_out <= '0'; -- 7seg 3 ena INACTIVE led_ena_out <= '0'; -- led ena INACTIVE END IF; END PROCESS; END behavior; The pinout for the transport control decode GAL is shown below: C16V8A __________________ nread_write_in =| 1| |20|* not used nlatch_in =| 2| |19|* not used addx_in_0 =| 3| |18|= seg7_1_ena_out addx_in_1 =| 4| |17|= seg7_2_ena_out addx_in_2 =| 5| |16|= btn_nena_out addx_in_3 =| 6| |15|= enc_nena_out addx_in_4 =| 7| |14|= seg7_3_ena_out addx_in_5 =| 8| |13|= led_ena_out addx_in_6 =| 9| |12|= nsense_out not used *|10| |11|* not used __________________	Table of Contents [Whole document in PDF 1.9MB] [more photos and information] Contents List of Figures List of Tables Executive Summary What Does the System do? Why Design and Implement this System? Project Goals Deliverables Conclusions Introduction Design Methodologies Application Analysis System Overview High-Level Hardware Specifications Control Board Mixer Unit Module-Level Hardware Specifications Control Board Mixer Unit Inter-Module Specifications Control Board Mixer Unit Digital Control Bus Hardware Schematics Control Board Mixer Unit Hardware Verification Control Board Mixer Unit Hardware PC Board Designs Control Board Mixer Unit Hardware Chassis Control Board Mixer Unit High-Level Firmware Design Control Board Mixer Unit The DACS Firmware Library Firmware Protocols Serial Communications Protocol Firmware Modules Firmware Library Control Board Mixer Unit Firmware Code Firmware Library, dacslib Control Board Mixer Unit High-Level Software Design Overall System: The Distributed Concept Functional Design Software Graphical User Interface Software Code MIDI Controller VHDL Code Control Board Mixer Unit Axiom MC68HC11 Single Board Computer References References Books Data Books and Data Sheets Web Sites About this document ...

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